This invention relates generally to a semiconductor device and more particularly, to a protection device in a metal insulator semiconductor (MIS) device such as an insulated gate field effect transistor (hereinafter called an "MOS transistor").
The construction and operation of a protection device in an MOS device will now be described with reference to FIGS. 1A and 1B.
In FIG. 1A, reference numeral 1 represents an input terminal, and reference numeral 2 represents a clamp resistance which is ordinarily composed of a diffusion layer or a polysilicon layer. Reference numeral 3 represents a surface breakdown type MOS transistor having the gate 4 thereof kept at a ground potential, and reference numeral 5 represents its drain. The drain terminal 5 is connected to the gate terminal 6 of an MOS transistor to be protected. As the voltage to be applied to the drain 5 is gradually increased in this circuit construction, an electric field crowds between the drain and the gate and finally, electrical breakdown occurs at the surface of the semiconductor substrate under the gate of the MOS transistor. After the breakdown, the current flows from the drain 5 to the ground through the substrate, and is limited by the resistance of the substrate.
Reference numerals 8 and 9 represent the drain and source of an MOS transistor 7. Generally, the surface breakdown voltage of the MOS transistor 3 is about 15 V.
As prior art references relating to gate protection, mention can be made of U.S. Pat. Nos. 3,555,374 and 3,999,212.
FIG. 1B shows the sectional structure of the protection device 101 shown in FIG. 1A. In the drawing, reference numeral 10 represents a p-type substrate, 12 is the input terminal 1 in FIG. 1A, and 102 is a clamp resistance formed by n.sup.+ diffusion. The MOS transistor represented by reference numeral 3 has a gate 17 consisting of polysilicon and drain and source consisting of n.sup.+ -type diffusion layers 15, 16. The members 17 and 16 are connected to the ground 18 while the member 15 is connected to the output 14 of a diffusion resistance 102, and hence to the gate of the active MOS device. Reference numeral 19 represents the gate oxide of the MOS transistor 3, and its structure and thickness are the same as those of the gate oxide of the active MOS device. Reference numeral 11 represents a thick insulation film for separating the devices.
The operation of the protection device will be explained for a case in which the gate oxide film 19 is 500 .ANG. thick, the breakdown voltage of the oxide film is 25 V, the surface breakdown voltage of the MOS transistor 3 is 15 V, a supply voltage of 5 V is applied to the drain 8 of the active MOS transistor 7, and its source is at the ground potential.
When a positive voltage is applied to the input terminal 1 and the voltage at the input terminal 5 of the active MOS device is above 15 V, the MOS transistor 3 undergoes breakdown, and a current flows through the ground terminal. If the resistance is 100 Ohms and the resistance 2 is 2 K Ohms after this breakdown, the voltage at which the gate insulation film of the active MOS device undergoes breakdown, that is, the input terminal voltage at which the voltage of the terminal 5 reaches 25 V, is found to be about 220 V by measurement.
When a negative voltage is applied to the input terminal 1, on the other hand, the p-type substrate 10 and the n.sup.+ -type diffusion layer 102 are a forward biased diode if the p-type substrate 10 is at the ground potential. Therefore a voltage applied to the gate oxide film 19 will not exceed a constant voltage of 0.6 V.
As described above, the protection device of the prior art exhibits a desirable effect in that the breakdown of the gate insulation film of the active MOS device is prevented. When it is used actually as one of the constituents for an IC (integrated circuit) or an LSI (large scale integrated circuit), however, various problems are encountered.
The first problem is as follows. The higher the value of the clamp resistance 2, the higher its effect because the clamp resistance 2 prevents the breakdown of the gate insulation film of the active MOS device by a high surface voltage applied thereto from outside. As shown in FIG. 2, however, the clamp resistance 2 is made of the same n.sup.+ -type diffusion layer as that forming the drain and source of the active MOS device, and its value is kept as low as possible in order not to deteriorate various characteristics of the active MOS device. When the value of the clamp resistance 2 is increased, therefore, the area of the resistance itself becomes greater.
The second problem is as follows. An external clock signal is applied to the input terminal 1 or to the input terminal 20 in FIG. 2. In ICs or LSIs in general, a signal having a TTL (Transistor-Transistor Logic) level or a low level of from 0 to 0.8 V and a high level of from 2.2 to 5 V is applied.
However, a clock pulse having a voltage swing, whose low level is below 0 V, e.g., from about -3 to about -5 V, and is below the potential (0 V) of the substrate 10, (clock signal having so-called "under-shoot") is applied from time to time depending upon the kind of the system to be employed. In this case, a parasitic bipolar device, which uses the source or drain formed by the n.sup.+ -type diffusion layer of the active MOS device as its collector, the p-type substrate as its base, and the resistance formed by the n.sup.+ -type diffusion layer as its emitter, operates. Although this parasitic operation is only temporary, if the active device is one of the elements of memory cells and the drain forms a storage node in this case, the stored data are destroyed.
The above is disclosed in Japanese Utility Model Laid-Open No. 188,364/1982, for example.
FIG. 2 shows one of the improved inventions made by the inventors of the present invention.
FIG. 2 shows the sectional structure of the protection device 101 in FIG. 1A and that of the internal circuit MOS transistor portion 102 to be protected. A CMOS structure is used by way of example. In the drawing, reference numeral 20 represents the input terminal, 21 is the clamp resistance, and 22 is a terminal which transmits a signal to the gates 33 and 34 of the internal circuit. The MOS transistor 3 in FIG. 1A is composed, in FIG. 2, of a gate 32, drain and source 23, 24 consisting of the n.sup.+ -type diffusion layer, and a p-type well 35 formed on the N-type substrate 37 as its substrate. The p-type diffusion layer 28 is kept fixed at the ground potential together with the gate and source 32, 24, and the drain 23 is connected to the terminal 22.
On the other hand, the active circuit 102 consists of a p-channel MOS transistor 44 whose source and drain are formed by the p-type diffusion layers 29, 30 and whose gate is represented by reference numeral 33, and an n-channel MOS transistor whose drain and source are formed by the n-type diffusion layers 26, 27 and whose gate is represented by reference numeral 34. The p-type well 36 is kept fixed at the ground potential through the p-type diffusion layer 31 together with the source 27, while the n-type substrate 37 is kept fixed at a power source (V.sub.cc) potential through the n-type diffusion layer 25 together with the source 29, with their drains 30 and 26 being connected to each other to form a so-called "CMOS inverter circuit".
Reference numeral 38 represents the gate insulator film (e.g., oxide film) of the MOS transistor 43, and its structure and thickness are the same as those of the gate insulator films 39, 40 of the active MOS transistors. The concentration and depth of the p-type well 35 are also the same as those of the p-type well 36 of the active MOS transistor 45.
The operation of the protection device will now be described with reference to the case in which the gate oxide films 38, 39 and 40 are 500 .ANG. thick, their breakdown voltage is 25 V, the surface breakdown voltage of the MOS transistor 43 formed by the drain 23, source 24 and gate 32 is 15 V, a power source voltage of 5 V is applied to the drain 41 of the active MOS transistor 45 and its source 27 is at the ground potential.
When a positive voltage is applied to the input terminal 20 and the voltage at the input terminal 22 of the active MOS transistor is above 15 V, the MOS transistor 43 undergoes breakdown, and a current flows through the ground terminal. If the resistance is 100 Ohms and the value of the clamp resistance 21 is 2 K Ohms after this breakdown, the voltage at which the gate of the active MOS transistor undergoes breakdown, that is, the value of the input terminal voltage necessary for the voltage of the terminal 22 to rise to 25 V, is found to be about 220 V by measurement.
On the other hand, when a negative voltage is applied to the input terminal 20, the member 35 and the n.sup.+ -type diffusion layer 23 are in diode connection in the forward direction if the p-type well 35 is at the ground potential. Therefore a voltage applied to the gate oxide films 39, 40 of the transistors 44, 45 will not exceed a constant voltage of about -0.6 V.
As described above, the protection device shown in FIG. 2 exhibits the desirable effect in preventing the breakdown of the gate insulator film of the active MOS transistor. When it is used in practice as one of the elements of an IC or an LSI, however, the following various problems are encountered.
The first problem is as follows. When the size of the MOS transistor is reduced, the gate insulator film must essentially be made thinner in order to sufficiently improve the transistor characteristics. However, when this is done the voltage value at which the gate of the active MOS transistor undergoes breakdown also drops. When the gate oxide film is made thinner, the surface breakdown voltage of the MOS transistor 43 tends to be reduced and this contributes to improving the breakdown voltage of the gate oxide film. However, it is obvious that the value of the breakdown voltage of the gate oxide film as viewed from the input terminal is lower than that of the prior art.
The second problem is as follows. High speed performance has been required recently for ICs and LSIs using MOS transistors, and examination has been made to improve the high speed performance of active circuits. In this sense, the delay time of an R-C circuit consisting of parasitic capacitance of the clamp resistance 21 and a wiring 22 interposed between the input terminal 20 and the transistor 43 has become a critical problem. When the value of the breakdown voltage of the gate oxide film as viewed from the input terminal is to be increased, the value of the clamp resistance 21 must be increased unavoidably, so that the delay time becomes greater and the high speed performance of the circuit is lost.